1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor memory device, and more particularly, to a method of fabricating a non-volatile memory device having trench isolation.
2. Discussion of the Related Art
Generally, semiconductor memory devices are categorized into a volatile memory device, which loses data in case of cutting off power supply, such as DRAM (dynamic random access memory) and SRAM (static random access memory) and a non-volatile memory device, which saves data in spite of cutting off power supply, such as a flash memory device.
The non-volatile memory device generally has a stacked gate configuration that floating and control gates are stacked on a semiconductor substrate in a vertical direction. A tunnel oxide layer is inserted between the floating gate and the semiconductor substrate. And, an ONO (oxide/nitride/oxide) layer is inserted between the floating and control gates.
In the non-volatile memory device having the stacked gate configuration, a trench isolation layer becomes more popular as a device isolation layer than a LOCOS layer to cope with the tendency of the increasing degree of integration of a device. In forming a non-volatile memory device having the trench isolation layer, trench isolation is preferentially carried out in a manner of forming an oxide layer pattern, a polysilicon layer pattern for a floating gate, and a nitride layer pattern on a semiconductor substrate, forming a trench in the semiconductor substrate, and filling the trench with an oxide layer. Subsequently, a stacked gate configuration or structure is then formed in a manner of removing the nitride layer pattern, forming an ONO layer, and forming a polysilicon layer for a control gate.
In the related art fabricating method, planarization is carried out on the oxide layer filling the trench. In doing so, the nitride layer is used as an etch stop layer.
However, wet etch should be performed to remove the nitride layer after completion of the planarization, whereby overall process steps are raised.
Moreover, the nitride layer pattern is removed using a H3PO4 solution, whereby the polysilicon layer pattern beneath the nitride layer pattern is damaged by the H3PO4 solution.